The power section of a three-level DC/AC converter (or "inverter") is known, for instance from the publication "A New Neutral-Point-Clamped PWM Inverter", in "IEEE Transactions on Industry Applications", Vol. IA-17, No. 5, September/October 1981, pages 518-521, and is shown in the first figure on page 518 of that publication.
One stage, i.e., that part of the inverter which provides one of the phase outputs of such a three-level inverter is also shown in the attached prior art FIG. 1. As shown in this prior art figure, the stage contains a series arrangement of four antiparallel circuits each having a semiconductor switching element and a bypass diode. As semiconductor switching elements, power MOS field-effect transistors or gate-turnoff thyristors ("GTO thyristors") are preferably used. If power field-effect transistors are used, the antiparallel bypass diode can be omitted because the inverse diode is frequently already provided internally to the component. In the stage shown in prior art FIG. 1, for instance, four GTO thyristors T11, T12, T21, T22 are used, across which the respective bypass diodes D11, D12, D21, D22 are shunted antiparallel. The first and second antiparallel circuit of T11, D11 and T12, D12 and the third and fourth antiparallel circuit of T21, D21 and T22, D22 represent the upper and lower parts respectively of the inverter stage shown.
The series arrangement of the four antiparallel circuits is fed via four connecting points from a d-c voltage source U.sub.D. The ends of the series arrangement are connected via switching-on relief choke coils to the positive and negative potential points 1, 2 of the d-c voltage source. In the example of prior art FIG. 1, these first and second switching-on relief choke coils are designated by L1 and L2. The other two connecting points correspond to the junction point between the first and the second antiparallel circuit and the junction point between the third and the fourth antiparallel circuit. These connecting points are coupled via first and second coupling diodes D1 and D2 and an inductance L10 that also serves as a switching-on relief choke coil, to the junction point of voltage divider capacitors C.sub.D1 and C.sub.D2. These voltage divider capacitors C.sub.D1, C.sub.D2 are also supplied by the d-c voltage source U.sub.D. The junction point between the second and the third antiparallel circuit serves as the output of the inverter stage, at which the stage voltage U.sub.P1 shown in FIG. 1, can be taken off. The switching-on relief choke coils L1, L2 and L10 need not always be present in the form of discrete components, depending on the first circuit design, but can instead be formed by means of parasitic line inductances.
In the attached FIG. 2, the principle of an exemplary switching cycle of the semiconductor switching elements of the inverter stage of FIG. 1 is schematically shown for generating an approximately sinusoidal phase output voltage U.sub.P1. In addition to a load connected to the phase output, load inductances that are present are utilized for smoothing the stage output voltages. For generating, for instance, a positive halfwave of the stage output voltage U.sub.P1, the thyristor T11 is switched on and off in pulse-fashion for a certain time. This is followed by a region in which thyristor T11 remains switched on and the thyristor T12 is switched on and off in pulse fashion. Finally, thyristor T12 remains switched off and thyristor T11 is actuated again in pulse fashion. A similar switching cycle for generating a negative halfwave is shown for the thyristor T121 and T22.
The ratio between the on and off time for each pulse of one of the thyristors can be varied by the well-known method of pulse-width modulation in such a manner that the phase output voltage is further approximated to the desired sinusoidal form. For greater clarity, modulation-related changes in the ratio of the respective on and off times are not shown in FIG. 2. In pulsing the semiconductor components T11 and T21 and the components T12 and T22, with the elements T11 and T21 respectively switched on, switching takes place between null potential and one-half potential and half and full potential of the d-c voltage source U.sub.D. This pulsing between three different potentials in the prior art three-level inverter makes possible an even more accurate approximation of the stage output voltage to the desired sinusoidal form than is the case in a known two-level inverter. There, switching takes place with pulse-width modulation only between null potential and the full potential of the feeding d-c voltage source.
In practice, the above-described pure power section of one stage of a three-level-inverter which contains in principle a series arrangement of four antiparallel circuits, two coupling diodes and switching-on relief chokes is incomplete to provide proper operation. Rather, it is advantageous to provide additional measures for switching-off relief especially for the semiconductor switching elements and their bypass diodes. For this reason, each of the antiparallel circuits in the example of FIG. 1, as well as each of the coupling diodes D1, D2, is provided with a known "RCD switching-off relief network".
It is also advantageous to isolate the semiconductor components and to remove the energy temporarily stored in the switching-on relief chokes L1, L2 and L10 during the switching-off process of the upper and lower part of an inverter stage. This purpose is served by two further additional RCD wiring networks of the elements C10, R10, D10 and C20, R20, D20. Each such network is between the junction point of the switching-on relief choke L1 or L2 and the respective end of the series arrangement and the junction point of the respective coupling diode D1 or D2 with the further switching-on relief choke L10.
A stage of the three-level-inverter wired with such RCD networks has the disadvantage that the cost of components required for the wiring is rather large and considerable losses occur in the wired circuits. The energies produced during the switching-off process of a semiconductor element are dissipated here in the ohmic resistance of the respective RCD network. The use of energy feedback circuits instead of the resistors in each of the RCD networks would further increase the cost of the components because each feedback circuit would have to feed back the energy from a different potential point into the d-c voltage source U.sub.D.
For the stages of two-level-inverters, wiring arrangements that are optimized for efficiency which use a minimum of components are already known. Thus, a circuit is shown in German Published Unexamined Patent Application 32 44 623, which is constructed entirely without RCD wiring networks and which has a switching-off relief capacitor, a storage capacitor, two switching-off relief diodes and a d-c consumer per inverter stage. The small losses produced by this wiring are reduced further if a d-c transformer is used for feeding back the energy into the d-c voltage source instead of an ohmic resistor.
Thus there is a need to provide wiring that is optimized as to efficiency for the semiconductor components in the stage of a three-level inverter which uses a minimum of components.